Various means of electrically and mechanically connecting, or coupling, an integrated circuit to a supporting substrate, or major substrate, are known. A common means used for this purpose are solder bumps disposed on the IC chip and the supporting substrate in a corresponding relationship such that their surfaces are parallel. An example of this is the Controlled Collapsed Chip Connection process, which is abbreviated as the "C4" or "C.sup.4 " process. The chip may be mounted to the supporting substrate such that the active surface of the chip, i.e., the structure which has the integrated components, faces away from the substrate or faces towards the substrate ("flip-chip"). In the first case, the signal and power lines from the active surface of the chip are brought to the periphery of the chip, and then connected to the supporting substrate by wirebonds or TAB circuits. In the latter case of a "flip-chip" orientation, conductive pads on the active surface of the IC chip contact solder bumps on the supporting substrate. Flip-chip bonding generally permits a greater quantity of interconnects per chip than other bonding approaches. The IC chip is bonded to the supporting substrate and held together by the fusing of corresponding solder bumps. The dimensions of such a solder bump are typically 3.2 mils (80 microns) high and 5 mils (125 microns) in diameter. In bonding, two opposing solder bumps are brought into registration and fused together to form a single solder bump spanning between the IC chip and the major substrate. The aspect ratio of the fused solder bump, i.e., the height of the structure divided by its width (diameter), is low, ranging between 1 and 2.
Each of the solder-bump connections must be able to withstand the mechanical shearing stresses that are developed by temperature fluctuations and the difference in thermal expansion coefficients between the IC chip and the supporting substrate during operation of the IC chip. Specifically, when the IC chip and the supporting substrate are exposed to elevated temperatures, they will expand at different rates and to different dimensions, thereby inducing mechanical stresses in the solder bump connections. After many thermal cycles and/or large changes in temperature, the fused solder bumps will begin to fatigue and develop cracks. This lowers or destroys the electrical conductivity of the fused solder bumps. The cracking usually occurs at the corners of the bases, or ends, of the fused solder bump. The cracking is exacerbated by the low fatigue resistance of solders typically used in IC manufacturing and the low aspect ratio of the fused solder bumps. With regard to the latter aspect, the rigidity of the fused solder bumps increases as the aspect ratio decreases, thereby lowering the amount of distance the midsection of the fused bumps may flex in order to absorb the applied stresses.
To reduce the thermal stresses, the IC chip and supporting substrate are often constructed from materials having closely matched expansion coefficients so that they expand to substantially the same dimensions when exposed to an elevated temperature. However, thermal stresses arc still generated each time the IC chip is "powered-up." When the chip is "turned on," a large transient temperature difference between the IC chip and the supporting substrate develops until the temperature of the supporting substrate reaches a temperature near that of the IC chip. Thus, with the high temperatures and power cycling common for high performance computer chips, solder bumps crack and become mechanically and electrically unreliable even when the IC chip and the supporting substrate have closely matched thermal expansion coefficients. This will become a greater problem in the future as computers are designed to dissipate more power in smaller volumes, thereby leading to greater thermal stresses.
One approach to addressing the fatigue problems of fused solder bumps is the Bonded Interconnect Process (BIP). The BIP process uses a gold (Au) bonding material, which is less easily fatigued, and provides a structure which has a larger aspect ratio, typically 4-8. (The aspect ratio is generally defined as the height divided by the width of the structure.) To form one BIP connection, a gold ball is formed on a pad of the IC chip, with a gold pin-like structure extending outward from the top of the gold ball. The gold ball and pin-like structure are formed in the same process by a thermal compression bonder, which has a hollow tip end. To form the ball and pin, the tip of the thermal compression bonder is placed in contact with the IC chip pad, the gold ball is smashed onto the pad to form the bond and the bonder tip is retracted from the surface to expose the wire, which is then cut to the desired length. The gold pin is brought in contact with a molten solder bump on a supporting substrate to form the BIP interconnect. At this point, the solder is flowed around the gold to form a solid mechanical connection. Generally, the gold ball and pin are intended to remain solid, i.e., to not fuse with, or melt into, the solder bump. The gold pin acts as a "stand-off" spacer between the IC chip and the supporting substrate, thereby increasing the aspect ratio of the BIP interconnect. However, under some conditions, the gold can dissolve into or react with the solder, which would weaken the holding capability of the solder. Gold-tin intermetallic compounds will also embrittle the joint.
Although the BIP process increases the reliability of the interconnect by having a higher aspect ratio and using gold at one end of the interconnect, the BIP process has a number of drawbacks which limit its use for IC chips having a large number of interconnects to the supporting substrate. First, the BIP process is an "invasive" process since the tip end of the compression bonder makes contact with, and actually compresses against, the IC chip. This places a substantial mechanical force against the IC chip which can destroy any active circuitry, such as transistors, underlying the pad on which the tip end makes contact. (The pad is large enough that the pad itself is not destroyed.) For low density integrated circuits (e.g., LSI), the active circuitry can be arranged such that the I/O pads do not overlay any active circuitry. However, for high density integrated circuits (e.g., VLSI and ULSI) used in high performance computers, I/O pads often overlay active circuitry. In some applications, the gold balls and pins are compressed onto the supporting substrate. Oftentimes, the supporting substrate also has circuitry which can be damaged by the thermo-compression bonder.
As a second disadvantage, the number of interconnects required for a high density device is large so that the number of BIP bonds required is similarly large. Each time a bond is made, i.e., the compression bonder contacts and compresses the chip, there is a risk of damage or fatigue. This risk multiplies with the number of bonds, thus reducing the yield of the BIP process. In view of the above two disadvantages, the BIP process in its currently used form is not compatible with many high-density IC chips. Further to this point, it is expected that the number of I/O pads per chip will continue to increase.
As a third disadvantage of the BIP process, the maximum number of BIP gold balls that can be formed currently is approximately 3 per second. With the current number of average I/O pads for typical ULSI circuits now approaching 500, it will take one thermo-compression bonder approximately 3 minutes to prepare one IC chip for bonding to the supporting substrate. In the future, it is expected that computer-system requirements will increase the number of I/O pads to well over 1000. This would increase the BIP preparation time to well over 5 minutes per single IC chip. Additionally, the number of IC chips requiring BIP connections for a high performance computer system is expected to grow from approximately 100 to well over 1000. These future trends raise concerns as to whether the BIP process can still be commercially feasibility for manufacturing high performance computer systems.
As a fourth disadvantage of the BIP process, the gold can dissolve into the solder during the heat contacting process, which can significantly weaken the holding capability of the solder due to the formation of inter-metallic compounds. The weakening reduces the reliability of the BIP interconnects and the reliability of systems using large numbers of BIP interconnects.
Another approach to addressing the fatigue problem of fused solder bumps is the UNIAX.TM. contact system. The UNIAX contact system is directed towards addressing the above-described disadvantages of the BIP process. In the UNIAX system, a plurality of cylindrical interconnect pins are held in a sheet of polymer film. Each interconnect pin is placed in a hole in the film such that its axial direction is held perpendicular to the film surface. The film is almost as thick as the axial length of the pin (100-200 microns). Each film hole holds its corresponding pin at the middle of its axial length such that a small and equal amount of the pin protrudes from either surface of the film. To interconnect the IC chip with the supporting substrate, the film is interposed between the chip and substrate, and the chip and substrate are lightly pressed together. The UNIAX pins are aligned to corresponding pads on both the chip and the substrate, and solder is used to mechanically couple the pins to the chip and substrate. Before contacting, the solder is deposited on each of the substrate and chip by any of the following means: evaporation through a shadow mask; defining a mask with photo-lithography followed by electroplating; metal lift-off; or stenciling or silkscreening a solder paste.
Although the UNIAX system has been successful at addressing some of the disadvantages of the C.sup.4 and BIP processes and, in theory, can provide a large number of interconnects, it also has drawbacks which limit its use for large numbers of interconnects. The aspect ratio of the UNIAX pins is on the order of 1 to 2. This creates a very stiff connection that will not flex under normal operating conditions. Any mismatch in thermal strain will put the UNIAX pin under stresses capable of causing the bond to fail. There is a tendency for the polymer film to limit the flexing of the UNIAX posts during thermal expansion and contraction. As a result, the mechanical sheer induced by thermal cycling are transferred to the solder joints at either end of each UNIAX pin, rather than being distributed along the axial direction of the pins. As a result, the UNIAX system may exhibit a reliability no better than that of the C.sup.4 solder bump process. A solderless pressure joint is possible with the UNIAX pin. The resistance of this type of contact is, however, unacceptably high in some cases.
In addition to these disadvantages, the C.sup.4, BIP, and UNIAX interconnect systems require large bonding pad areas on the IC chip and/or the substrate, usually 100 .mu.m or more on a side or 100 .mu.m or more in diameter. The large pad areas not only limit the number of interconnects that can be made to the chip and substrate but increase the parasitic capacitance of the interconnect. As is known in the semiconductor art and circuit board art, the amount of parasitic capacitance of a pad is proportionally related to its area, and the speed at which the interconnect can transmit electrical signals decreases with increasing parasitic capacitance. The current trends in high performance computer systems are towards increasing the density of chip interconnects and speed of electrical communications. These trends raise concerns as to whether the C.sup.4, BIP, and UNIAX approaches can still be used for manufacturing high performance computer systems.
Presently, there is a need for a high density, high speed interconnect structure whose characteristics match or exceed the non-invasive bonding of fused solder bumps and the higher mechanical and electrical reliability of BIP, and which can be easily manufactured with low parasitic capacitance, such that several hundred to several thousand interconnects can be made from a one centimeter square chip to a supporting substrate. The present invention is directed to filling this need.